Logic Analyzer Ver. 1.0 (a.k.a. "logan")

• Logan is a very low cost, PC controlled logic analyzer. Total cost in parts is around $40CND, much less if you've got certain things on hand (project box, cables, DB9 connector, etc.).
  In it's most basic form it is simply a glorified RAM buffer, samples are stored in a large RAM. A PIC Microcontroller acts as the "controller", controlling the CPLD, RAM and input buffer.
  Max sample rate is in the 4MHz to a theoretical ~40MHz range.

What does it consist of?

• Logan consists of 4 major components:
  
  
  1. Microchip PIC16F877 4MHz Microcontroller
  2. Xilinx XC9536 CPLD
  3. Dallas DS1258Y NV 256KB RAM chip
  4. 74LS245 Octal Buffer Chips x2
  
  Obviously other support components are required, including a variety of capactors, a 4MHz crystal, and a MAXIM rs232 level convertor chip. Please see schematic for components required.
  
  A way to get a programmed PIC is also required. If you have or have access to a programmer a HEX file can be found below.
  If on the other hand you have no access to a programmer a preprogrammed PIC can be purchased from me. Please click here for further details.
  
  The CPLD must also be programmed. A bit file is available below.
  Unfortunately I do not have the facilities to program the CPLD, however simple programmers you can build are available on the net.
  The code for the CPLD was compiled using the free CPLD environment available from Xilinx.
  
  And finally, the Logic Analyzer Client must also be compiled.
  The client was written using Borland C Builder Ver. 3.0.
  A compiled version that should work on most windows system is available below.
  For other systems the project can't be directly compiled, I've included my source code below and it should give good pointers on porting it to other OSs.

What does it do?

• On powerup, Logan makes a few self checks, and then sits waiting to receive a character from the serial port.
  
  On receipt of a command from the client software over the serial port it performs the requested action.
  
  For example, if an "s" command is received it sets bits on the size bus to correspond to what is requested; the CPLD uses these lines to determine what sample depth is required.
  
  The commands the PIC recognizes are:
  • d - dump_mem - prints out the contents of the memory until done is received, terminal friendly, used for testing
  • w - write_mem - writes to the memory a pseudo random number, used for testing
  • s - set_size - prompts for number between 0-7 and sets the size bits accordingly
  • c - set_clock - prompts for number between 0-7 and sets the clock bits accordingly
  • r - read_mem - reads the memory, sending it as full binary
  • t - store - sets clk_sel, rd_strb and finally RST to start a data capture, waits for done from CPLD
  • l - load_trigger - loads trigger supplied by serial port into global variables
  
  Triggering is completely optional.
  If triggering is disabled, then on receipt of a "store" command the PIC tells the CPLD to start capturing and waits for the CPLD to signal that capturing has been completed.
  
  If a trigger has been loaded things proceed a little differently.
  • The PIC sets everything up to start a "store", however it holds the CPLD in reset.
  • The PIC then starts monitoring the data bus for the trigger condition
  • The following section of code is a 2 state, state machine. So if a trigger on a level is wanted both states look for the same logic value.
    If an edge is wanted instead the first state looks for a "0" and the second state looks for a "one"
  • Once the state machine has passed through the second state capturing of the waveform begins, and the PIC waits for the CPLD to signal completion of capture.